Optimized inverter design of ring oscillator based wafer-level TSV connectivity test (RO-TSV-CT)

Optimization of inverter design for ring oscillator based wafer-level TSV connectivity test (RO-TSV-CT) scheme is proposed. Since RO-TSV-CT is based on ring oscillator, it contains many inverters, is located to TSVs and input/output circuitries (I/Os) very closely. Therefore the inverters should be designed so as not to consume on-chip I/O design area, not to have complex power supply network, and not to give parasitic capacitance loading to I/Os. Especially, it should give a very effective and accurate test result. This paper shows the optimization results based on TSMC 0.18 um technology.