DocumentCode :
3437413
Title :
A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application
Author :
Rahul, T. ; Sahoo, B. ; Arya, S. ; Parvathy, S.J. ; Vulligaddala, V.B.
Author_Institution :
Amrita Vishwa Vidyapeetham Univ., Kochi, India
fYear :
2015
fDate :
3-7 Jan. 2015
Firstpage :
265
Lastpage :
270
Abstract :
This paper proposes a wide dynamic-range lowpower signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slewrate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA.
Keywords :
CMOS integrated circuits; analogue-digital conversion; delta-sigma modulation; electric current measurement; electric sensing devices; flicker noise; integrated circuit noise; operational amplifiers; programmable circuits; sampling methods; signal conditioning circuits; switched capacitor networks; AMS CMOS process; analog-to-digital converter; closed loop SC-PGA architecture; current 2 mA; double sampling technique; flicker noise; gain 80 dB; level-shifting circuit; low-side current sensing application; multibit second order ΔΣ-ADC design; offset noise; op amp; rail-to-rail input common mode; settling requirement; size 0.35 mum; slew- rate requirement; supply voltage variation; switched capacitor programmable gain amplifier; voltage 3.3 V; wide dynamic-range low-power signal conditioning circuit; Capacitors; Clocks; Electronics packaging; Gain; Noise; Operational amplifiers; Sensors; Low-side current sensing; PGA; double sampling; second-order ΔΣ-ADC;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2015.51
Filename :
7031744
Link To Document :
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