Title :
The influence of the SiN cap process on the electromigration and stressvoiding performance of dual damascene Cu interconnects
Author :
von Glasow, A. ; Fischer, A.H. ; Bunel, D. ; Friese, G. ; Hausmann, A. ; Heitzsch, O. ; Hommel, M. ; Kriz, J. ; Penka, S.S. ; Raffin, P. ; Robin, C. ; Sperlich, H.-P. ; Ungar, F. ; Zitzelsberge, A.E.
Author_Institution :
Infineon Technol. AG, Munich, Germany
fDate :
30 March-4 April 2003
Abstract :
The influence of the SiN cap-layer deposition process including different pre-clean treatments on the electromigration (EM) and stressvoiding (SV) behavior of copper dual damascene metallizations has been studied. A remarkable trade-off between the EM and SV performance was revealed depending primarily on the pre-treatment before cap-layer deposition rather than the deposition process itself. On the one hand, an "aggressive" pre-treatment yields improved Cu/SiN-interface properties with higher electromigration failure times and activation energies (1.22-1.26 eV). However, these pre-cleans were found to provoke stressvoiding failures because of the recovery of crystal defects induced in the bulk copper during the plasma treatment. The degree of microstructural damage and hence the SV susceptibility were found to increase with the preclean intensity. In contrast, no SV risk is related to "less aggressive" pre-clean treatments since they influence only the copper surface. The crystal structure of the bulk remains unaffected and hence, in the absence of any crystal recovery, no vacancies are generated. However, these pre-cleans result in significantly lower EM performance with smaller failure times and activation energies (1.03-1.06 eV). The results illustrate the need to adjust the SiN cap-layer process parameters with respect to both EM and SV performance to meet the overall reliability requirements for these wear-out mechanisms at the same time.
Keywords :
copper; electromigration; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; plasma CVD; plasma materials processing; silicon compounds; surface treatment; voids (solid); 1.03 to 1.06 eV; 1.22 to 1.26 eV; Cu; Cu-SiN; Cu/SiN-interface properties; SiN cap process; aggressive pre-treatment; crystal defect recovery; dual damascene Cu interconnects; dual damascene metallizations; electromigration activation energies; electromigration failure times; electromigration performance; microstructural damage; plasma treatment; pre-clean treatments; reliability requirements; stressvoiding failures; stressvoiding performance; vacancy generation; wear-out mechanisms; Adhesives; Bonding; Copper; Crystal microstructure; Electromigration; Mechanical factors; Plasma properties; Silicon compounds; Surface cleaning; Surface treatment;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197735