DocumentCode
3437480
Title
Stress-induced voiding and its geometry dependency characterization
Author
Doong, K.Y.Y. ; Wang, R.C.J. ; Lin, S.C. ; Chiu, C.C. ; Su, Donglin ; Wu, Kaijie ; Young, K.L.
Author_Institution
Taiwan Semicond. Manuf. Co., Hsin-Chu, Taiwan
fYear
2003
fDate
30 March-4 April 2003
Firstpage
156
Lastpage
160
Abstract
Stress induced voiding (SIV) is explored from the aspects of design attribute and geometry parameters. Two kinds of test structures were used to evaluate resistance change in relation to reliability and to understand the SIV mechanism. Thus, a reliability-robustness guideline from a consideration of geometry configuration can be derived.
Keywords
copper; failure analysis; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; voids (solid); Cu; Cu damascene; SIV failure; design attribute; geometry configuration; geometry dependency characterization; metal aspect ratios; relative failure frequency; reliability; reliability-robustness guideline; stress-induced voiding; test structures; Failure analysis; Geometry; Guidelines; Joining processes; Lead; Manufacturing industries; Semiconductor device manufacture; Testing; Thermal resistance; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN
0-7803-7649-8
Type
conf
DOI
10.1109/RELPHY.2003.1197737
Filename
1197737
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