The capability mechanism of a VLSI processor

The authors describe the capability mechanism of a VLSI-based processor that is free from the problems that had plagued earlier capability-based designs. They examine architecture of a VLSI processor that employs a RISC reduced-instruction-set-computer)-like execution unit and a microcoded coprocessor for storage management and relatively complex capability-related operations. The use of a novel technique for creating small object dynamically in the architecture results in protected procedure call times close to (unprotected) call times in conventional machines. The use of `flat´ name-space for objects results in fast capability translation and zero swapping overhead