DocumentCode
3437527
Title
Berger check prediction for concurrent error detection in the Braun array multiplier
Author
Jones, Christian Martyn ; Dlay, Satnam Singh ; Naguib, Raouf Gorgui
Author_Institution
Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
Volume
1
fYear
1996
fDate
13-16 Oct 1996
Firstpage
81
Abstract
We develop the Berger Check Symbol Prediction and report the performance benefit for the realisation of practical concurrent error detection systems. Furthermore, we show that the Berger coded Braun array multiplier can not only achieve the objective for detecting unidirectional faults but analysis has indicated an inherent ability of this prediction technique for error detection beyond the scope for which it was originally intended. In fact the coding provides error detectability for single and multiple stuck at faults. Further study suggests the performance of the Berger check prediction Braun array multiplier tends towards 100% error detectability for increasing input bit length and array dimensions. The Berger check predictive Braun array multiplier has introduced a high level of concurrent error detectability with only a minimal extension in the hardware implementation
Keywords
arithmetic codes; digital arithmetic; error detection codes; fault diagnosis; logic arrays; logic testing; multiplying circuits; ALU error detection; Berger check symbol prediction; Braun array multiplier; concurrent error detection; multiple stuck at faults; single stuck at faults; unidirectional fault detection; Arithmetic; Circuit faults; Cryptography; Decoding; Design engineering; Fault detection; Hardware; Logic arrays; Logic design; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
Conference_Location
Rodos
Print_ISBN
0-7803-3650-X
Type
conf
DOI
10.1109/ICECS.1996.582691
Filename
582691
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