Title :
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
Author :
Heck, Guilherme ; Heck, Leandro S. ; Singhvi, Ajay ; Moreira, Matheus T. ; Beerel, Peter A. ; Calazans, Ney L. V.
Author_Institution :
Pontificia Univ. Catolica do Rio Grande do Sul, Porto Alegre, Brazil
Abstract :
We present the design and analysis of three commonly used types of programmable delay elements suitable for use in 2-phase bundled-data asynchronous circuits. Our objective is to minimize power consumption and delay margins needed for correct operation under voltage scaling. We propose both circuit design and transistor sizing strategies to optimize these elements and discuss the relative trade-offs observed in a 65 nm bulk CMOS technology.
Keywords :
CMOS logic circuits; asynchronous circuits; circuit optimisation; delay circuits; power consumption; 2-phase bundled-data asynchronous circuits; bulk CMOS technology; circuit design; delay margins; power consumption; programmable delay elements; size 65 nm; transistor sizing strategy; voltage scaling; Delay lines; Delays; Inverters; Logic gates; MOS devices; Propagation delay; Transistors; 2-phase bundled-data; Asynchronous circuits; Delay elements; Voltage scaling;
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
DOI :
10.1109/VLSID.2015.60
