Optimum clock slope for flip-flops within a clock domain: Analysis and a case study

In this paper, the impact of clock slope specification on the energy consumption of a clock domain is analyzed. Results show that the clock slope requirement can be relaxed at the cost of a very small speed penalty and energy increase in the flip-flops (FFs). On the other hand, relaxing the clock slope specification allows for downsizing the local buffers driving the FFs that belong to the same clock domain. From the energy point of view, an optimum clock slope is found that leads to energy savings of 30 ÷ 40% compared to the usually adopted clock slopes. The effectiveness of the clock slope optimization, including the impact on local skew/jitter sources, is discussed for the typical case of Master-Slave FFs by resorting to simulations on a 65-nm CMOS technology.