Design and implementation of multiple cryptographic algorithm interface circuit based on secure SoC

Based on the requirements of integrating multiple cryptographic algorithm IP cores into secure SoC, after analyzing the existing design of interface circuit, an interface circuit of the multiple cryptographic algorithm IP core is designed and implemented in this paper. Using the bridge technology, it achieves the dynamic reconfiguration of three cryptographic algorithm IP cores—AES, ECC and SHA1 tied to one dual-port RAM, as well as interconnection with the MCU. It not only effectively solves the inconsistent of the operation frequency and the interface data width of the multiple cryptographic algorithm IP cores, but also increases interior resource utilization rate of secure SoC and cryptographic service speed, obtaining excellent cost performance.