Impact of scaling on the high current behavior of RF CMOS technology

Author

Boselli, Gianluca ; Reddy, Vijay ; Duvvury, Charvaka

Author_Institution

Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

229

Lastpage

234

Abstract

In this paper the impact of the starting material resistivity on the ESD, latch-up and BVii sensitivity is investigated for a sub-0.1 μm fully silicided CMOS technology for low power and RF applications. The mechanisms through which a substrate spreading resistance increase enhances the uniformity of the ESD current in nMOS protection methods are investigated in detail.

Keywords

CMOS integrated circuits; MOSFET; electrostatic discharge; integrated circuit reliability; low-power electronics; protection; radiofrequency integrated circuits; semiconductor device breakdown; 90 nm; ESD current uniformity; RF CMOS technology; breakdown voltage injection induced sensitivity; high current behavior; latch-up; low power applications; nMOS protection methods; scaling; starting material resistivity; sub-0.1 μm fully silicided CMOS technology; substrate spreading resistance increase; CMOS technology; Conductivity; Electrostatic discharge; Equations; Instruments; MOS devices; MOSFETs; Materials testing; Radio frequency; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197750

Filename

1197750