Internal behavior of BCD ESD protection devices under very-fast TLP stress

Author

Blaho, M. ; Pogany, Dionyz ; Gornik, E. ; Zullino, Lucia ; Morena, E. ; Stella, Roberto ; Andreini, Antonio

Author_Institution

Inst. for Solid State Electron., Vienna Univ. of Technol., Austria

fYear

2003

fDate

30 March-4 April 2003

Firstpage

235

Lastpage

240

Abstract

BCD electrostatic discharge (ESD) protection npn devices with and without a sinker are analyzed experimentally and by device simulation. The device internal thermal and free carrier density distributions during vf-TLP and TLP stresses are studied by a backside transient interferometric mapping technique. Experimentally observed activity of lateral and vertical parts of the npn transistor are well reproduced by the simulation.

Keywords

electron density; electrostatic discharge; failure analysis; high-speed techniques; light interferometry; power bipolar transistors; protection; pulse measurement; semiconductor device models; semiconductor device reliability; semiconductor device testing; temperature distribution; BCD ESD protection devices; BCD electrostatic discharge protection npn devices; backside transient interferometric mapping technique; charged device model; device simulation; internal behavior; internal free carrier density distributions; internal thermal distributions; npn transistor; optical interferometry; sinker; very-fast TLP stress; very-fast transmission line testing; Analytical models; Biological system modeling; Electrostatic discharge; Electrostatic interference; Internal stresses; Optical interferometry; Optical pulses; Power system transients; Protection; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197751

Filename

1197751