• DocumentCode
    3437780
  • Title

    Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis

  • Author

    Hajimiri, H. ; Rahmani, K. ; Mishra, P.

  • Author_Institution
    Dept. of Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL, USA
  • fYear
    2015
  • fDate
    3-7 Jan. 2015
  • Firstpage
    369
  • Lastpage
    374
  • Abstract
    Estimation of peak power consumption is an essential task in order to design reliable systems. Optimistic design choices can make the circuit unreliable and vulnerable to power attacks, whereas pessimistic design can lead to unacceptable design overhead. The power virus problem is defined as finding input patterns that can maximize switching activity (dynamic power dissipation) in digital circuits. In this paper, we present a fast and simple to implement power virus generation technique utilizing a probabilistic cost-benefit analysis. To maximize switching activity, our proposed algorithm iteratively enables transitions in high fan-out gates while considering the trade-off between switching of new gates (benefit) and blocking of gate transitions in the future iterations (cost) due to switching of the currently selected one. Extensive experiments using both combinational and sequential benchmarks demonstrate that our approach can achieve up to 64% more toggles (30.7% on average) for zero-delay model and improvements of up to 319% (109% on average) for unit-delay model compared to the state-of-the-art techniques.
  • Keywords
    circuit reliability; combinational circuits; cost-benefit analysis; logic design; logic gates; power consumption; probability; sequential circuits; combinational benchmark circuit; digital circuits; dynamic power dissipation; gate transition blocking; high fan-out gates; optimistic design; peak power consumption estimation; power attacks; power virus generation technique; probabilistic cost-benefit analysis; sequential benchmark circuit; switching activity; zero-delay model; Estimation; Integrated circuit modeling; Logic gates; Power demand; Switches; Switching circuits; Vectors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2015 28th International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2015.68
  • Filename
    7031762