Dynamic substrate resistance snapback triggering of ESD protection devices

This paper describes a novel approach to design self-triggered ESD protection structures. It consists in adding a reverse biased p-n junction in the path of the current, flowing into the base of the ESD activated parasitic BIT device. As a result, the base resistance of the parasitic BIT is increased, which in turn leads to faster and more uniform snapback triggering. The ESD threshold levels for the investigated structures designed in the new approach are found to increase. MEDICI simulations, in combination with TLP and EMMI characterization are performed to study the structure operation.