Process variation-aware floorplanning for 3D many-core processors

Author

Hyejeong Hong ; Jaeil Lim ; Sungho Kang

Author_Institution

Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea

fYear

2012

fDate

9-11 Dec. 2012

Firstpage

193

Lastpage

196

Abstract

Thermal management is one of the critical issues in 3D many-core processors design. 3D many-core floorplanning has so far focused on only the configuration of cores and memories across layers. However, 3D floorplanning should also take die stack ordering into account because the characteristics of dies may vary due to growing process variations. A new 3D floorplanning approach which covers die stack ordering is proposed. The evaluation shows that peak steady state temperature is reduced by about 2 K without any overhead in manufacturing process.

Keywords

integrated circuit design; integrated circuit layout; integrated circuit manufacture; multiprocessing systems; thermal management (packaging); 3D floorplanning; 3D many-core floorplanning; 3D many-core processors design; die stack ordering; manufacturing process; memories across layers; peak steady state temperature; process variation-aware floorplanning; temperature 2 K; Memory management; Multicore processing; Power demand; Program processors; Stacking; Steady-state; Thermal management;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE

Conference_Location

Taipei

Print_ISBN

978-1-4673-1444-2

Electronic_ISBN

978-1-4673-1445-9

Type

conf

DOI

10.1109/EDAPS.2012.6469421

Filename

6469421