DocumentCode :
3437961
Title :
A hybrid architecture for Hopfield neural networks and its GaAs implementation using CCDs as storage elements
Author :
Chen, L. ; Wedlake, M. ; Deliyannides, G. ; Kwok, H.H.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
Volume :
2
fYear :
1995
fDate :
15-16 May 1995
Firstpage :
445
Abstract :
A hybrid architecture for Hopfield artificial neural networks and its GaAs implementation are described in this paper. This approach merges parallel summation and multiplication and serial neuron state updating. For a N×N network, only N multipliers and one neuron activation function are needed
Keywords :
Hopfield neural nets; III-V semiconductors; charge-coupled device circuits; gallium arsenide; neural chips; neural net architecture; CCD storage elements; GaAs; Hopfield artificial neural network; hybrid architecture; neuron activation function; parallel multiplication; parallel summation; serial neuron state updating; Artificial neural networks; Charge coupled devices; Computer architecture; Gallium arsenide; Hopfield neural networks; Neural networks; Neurons; Nonvolatile memory; Parallel architectures; Power dissipation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
WESCANEX 95. Communications, Power, and Computing. Conference Proceedings., IEEE
Conference_Location :
Winnipeg, Man.
Print_ISBN :
0-7803-2725-X
Type :
conf
DOI :
10.1109/WESCAN.1995.494071
Filename :
494071
Link To Document :
بازگشت