Title :
The influence of process and design of subcollectors on the ESD robustness of ESD structures and silicon germanium heterojunction bipolar transistors in a BiCMOS SiGe technology
Author :
Voldman, Steven H. ; Lanzerotti, Louis ; Ronan, Brian ; St Onge, S. ; Dunn, Jim
Author_Institution :
IBM Microeletronics, Essex Junction, VT, USA
fDate :
30 March-4 April 2003
Abstract :
This paper demonstrates the effect of process and design variations on the ESD robustness of both active and passive elements in 50, 120 and 200 GHz BiCMOS SiGe HBT processes. The influence of subcollector dopant type and concentration, and n-well on ESD robustness of SiGe HBT npn transistors, SiGe varactor structures, p+/n-well/subcollector structures and n-well diode structures is shown. HBM and TLP ESD measurements are provided to evaluate the observation of lateral resistor ballasting in the subcollector region in these structures and its influence on ESD robustness.
Keywords :
BiCMOS integrated circuits; Ge-Si alloys; electrostatic discharge; heterojunction bipolar transistors; integrated circuit reliability; ion implantation; semiconductor device models; semiconductor device reliability; semiconductor materials; 50 to 200 GHz; BiCMOS SiGe technology; ESD robustness; ESD structures; HBM ESD measurements; SiGe; SiGe HBT npn transistors; SiGe HBT processes; SiGe varactor structures; TLP ESD measurements; active elements; design variations; heterojunction bipolar transistors; latchup; lateral resistor ballasting; n-well diode structures; p+/n-well/subcollector structure; passive elements; physical incremental model; process variations; subcollector design; transmission line pulse; BiCMOS integrated circuits; Diodes; Electrostatic discharge; Germanium silicon alloys; Heterojunction bipolar transistors; Process design; Resistors; Robustness; Silicon germanium; Varactors;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197772
