DRAM reliability characterization by using dynamic operation stress in wafer burn-in mode

Author

Kim, Il-Gweon ; Choi, Sc-Kyeong ; Choi, Jin-Hyeok ; Park, Joo-Seog

Author_Institution

Inst. of Ind. Sci., Univ. of Tokyo, Japan

fYear

2003

fDate

30 March-4 April 2003

Firstpage

361

Lastpage

365

Abstract

Circuits to apply dynamic operation stress (DOS) to DRAM cells in wafer burn-in (WBI) mode are successfully implemented and contribute to wafer level reliability characterization of DRAMs. We verify that DOS during the burn-in (BI) test deteriorates data retention time microscopically, which is mainly attributed to DOS-induced hot carrier (HC) degradation of DRAM cells. In addition, the DRAM reliability characterization results in the WBI mode are in good agreement with those by dynamic operation in the package burn-in (PBI) mode.

Keywords

CMOS memory circuits; DRAM chips; failure analysis; hot carriers; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; 0.15 micron; DRAM reliability characterization; burn-in test; data retention time; dynamic operation stress; hot carrier degradation; package burn-in mode; wafer burn-in mode; wafer level reliability characterization; Bismuth; Capacitors; Circuit testing; Dielectrics; Electron traps; Packaging; Random access memory; Thermal degradation; Thermal stresses; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197774

Filename

1197774