Title :
The effect of NBTI on 3D integrated circuits
Author :
Cheng-Hong Lin ; Yi-Chang Lu ; Chin-Khai Tang ; Kuen-Yu Tsai
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
Thermal-induced reliability problem can be very severe in 3D ICs. In this paper, Negative Bias Temperature Instability (NBTI) effect is addressed. We first propose an NBTI-aware simulation flow for 3D ICs. Using the flow and the MIPS789 benchmark circuit as an example, we demonstrate how we can evaluate digital 3D IC performance under NBTI. By comparing simulation results, we recommend to place critical gates on the layer close to the heat sink in order to lower peak temperature and NBTI impacts. The proposed floor plan can make peak temperature 20 °C lower and NBTI impact 2.4% less when compared to the one using homogeneous stacking.
Keywords :
circuit layout; heat sinks; negative bias temperature instability; three-dimensional integrated circuits; 3D IC performance; 3D integrated circuit; MIPS789 benchmark circuit; NBTI aware simulation flow; NBTI impact; floor plan; heat sink; homogeneous stacking; negative bias temperature instability; thermal induced reliability problem; Degradation; Delay; Floors; Heat sinks; Integrated circuit modeling; Logic gates; Temperature sensors;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE
Conference_Location :
Taipei
Print_ISBN :
978-1-4673-1444-2
Electronic_ISBN :
978-1-4673-1445-9
DOI :
10.1109/EDAPS.2012.6469435
