The Astronautics ZS-1 processor

Author

Smith, J.E. ; Dermer, G.E. ; Vanderwarn, B.D. ; Klinger, S.D. ; Rozewski, C.M. ; Fowler, D.L. ; Scidmore, K.R. ; Laudon, J.P.

Author_Institution

Astronaut. Corp. of America, Madison, WI, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

307

Lastpage

310

Abstract

The Astronautics ZS-1 is a high speed minisupercomputer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture which splits instruction words into two streams, one for fixed-point/memory-address computation and the other for floating-point operations. The two instruction streams are then processed in parallel, with architectural queues providing communication between the streams. Pipelining is used extensively throughout the ZS-1. The combination of decoupling and pipelining provides overall, sustained performance of about one third a CRAY-XMP-1 on compiled double-precision Fortran. The authors give a description of the decoupled architecture and discuss other forms of parallelism used in the ZS-1. A discussion of static and dynamic instruction scheduling is also included

Keywords

minicomputers; parallel processing; Astronautics ZS-1 processor; decoupled architecture; fixed-point/memory-address computation; floating-point operations; instruction scheduling; instruction streams; minisupercomputer system; Application software; Central Processing Unit; Computer architecture; Decoding; Design engineering; Hardware; Logic; Parallel processing; Pipeline processing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25712

Filename

25712