• DocumentCode
    3438237
  • Title

    Practical WLRC methodology & applications in a wafer foundry

  • Author

    Chien, W. T Kary ; Chiang, Shunwang ; Tseng, Summer ; Huang, Charles H J ; Yang, Kelly ; Wang, Willings ; Zhou, Joyce

  • Author_Institution
    Reliability Eng., Semicond. Manuf. Int. Corp., Shanghai, China
  • fYear
    2003
  • fDate
    30 March-4 April 2003
  • Firstpage
    395
  • Lastpage
    401
  • Abstract
    As the product life cycle shrinks, qualification needs to be completed in a much shorter time. This makes wafer level reliability (WLR) an important tool, enabling results to be obtained in a much shorter time. The two key issues for WLR are to guarantee the same failure mechanisms as conventional package-level reliability (PLR) and to maintain a statistically acceptable correlation (in terms of parameter estimation, lifetime projections and trend). We report the correlation of WLR and PLR tests and present WLR control (WLRC) methodology to ensure in-line reliability/process stability and to assist new technology development. We also present WLRC cases/plots/models, which show the benefits of a special control chart and principal component analysis (PCA). Apart from its use for in-line monitoring, by suitably designing the test structures and choosing the fail criteria, we also apply WLRC as a quick assessment of process/tool change qualification. WLRC can be embedded in the wafer acceptance test (WAT). We show how to use WLRC data to formulate reliability-WAT-yield models to facilitate yield improvement and reliability optimization.
  • Keywords
    electromigration; failure analysis; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; integrated circuit yield; principal component analysis; process monitoring; WLR control methodology; WLRC methodology; control chart; fail criteria; failure mechanisms; lifetime projections; package-level reliability; parameter estimations; principal component analysis; process stability; product life cycle; reliability optimization; reliability-WAT-yield models; statistically acceptable correlation; test structures; wafer acceptance test; wafer foundry; wafer level reliability; yield improvement; Failure analysis; Foundries; Maintenance; Packaging; Parameter estimation; Principal component analysis; Qualifications; Stability; Testing; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
  • Print_ISBN
    0-7803-7649-8
  • Type

    conf

  • DOI
    10.1109/RELPHY.2003.1197780
  • Filename
    1197780