A proposed standard test bus and boundary scan architecture

Author

Whetsel, Lee

Author_Institution

Texas Instrum. Inc., Plano, TX, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

330

Lastpage

333

Abstract

The author describes the test interface and boundary scan architecture proposed in the Joint Test Action Group (JTAG) 2.0 specification. The test access port described in the JTAG specification meets the requirements for a standard serial test interface. The architecture is flexible enough to support test structures ranging from boundary scan to the sophisticated maintenance and support structures required in the high end military and commercial arena of the electronics industry. Features discussed include the test access port, the instruction register, and the data register

Keywords

circuit CAD; computer interfaces; integrated circuit testing; standards; Joint Test Action Group 2.0 specification; boundary scan architecture; data register; instruction register; serial test interface; standard test bus; test access port; Application specific integrated circuits; Circuit testing; Electronic equipment testing; Electronics industry; Integrated circuit testing; Logic testing; Manufacturing; Military standards; Standardization; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25716

Filename

25716