DocumentCode
3438313
Title
High speed, low power CMOS transmitter-receiver system
Author
Gabara, Thaddeus J. ; Thompson, David W.
Author_Institution
AT&T Bell Labs., Allentown, PA, USA
fYear
1988
fDate
3-5 Oct 1988
Firstpage
344
Lastpage
347
Abstract
A CMOS transmitter-receiver system is described which has a limited voltage swing output. This system has high performance and low power dissipation. The measured worst-case frequency occurs near the 200-MHz range while the ADVICE projected best-case fast frequency is 600 MHz. This system also has the capability of functioning down to DC
Keywords
CMOS integrated circuits; data communication systems; 600 MHz; CMOS transmitter-receiver system; low power dissipation; Clocks; Delay; Frequency; Power dissipation; Power transmission lines; Pulse circuits; Resistors; Timing; Transmitters; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location
Rye Brook, NY
Print_ISBN
0-8186-0872-2
Type
conf
DOI
10.1109/ICCD.1988.25719
Filename
25719
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