Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs

Author

Tahui Wang ; Tsai, C.W. ; Chen, Meng Chang ; Chan, C.T. ; Chiang, Huihua K.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan

fYear

2003

fDate

30 March-4 April 2003

Firstpage

437

Lastpage

441

Abstract

Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4 nm) pMOS is observed. This result is believed to be due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of the substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.

Keywords

MOSFET; dielectric thin films; failure analysis; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; silicon-on-insulator; tunnelling; 1.4 nm; PD-SOI devices; breakdown induced carrier heating; breakdown progression; floating substrate devices; forward-biased substrate devices; gate oxide reliability; hole stress current; hole tunneling current; negative substrate bias enhanced breakdown hardness; numerical analysis; substrate bias effect; ultra-thin oxide pMOSFETs; Breakdown voltage; Circuits; Electric breakdown; Heating; Leakage current; MOSFETs; Numerical analysis; Stress; Sun; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197787

Filename

1197787