DocumentCode :
3438376
Title :
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs
Author :
Tajammul, M.A. ; Jafri, S.M.A. ; Ellerve, P. ; Hemani, A. ; Tenhunen, H. ; Plosila, J.
Author_Institution :
R. Inst. of Technol., Stockholm, Sweden
fYear :
2015
fDate :
3-7 Jan. 2015
Firstpage :
547
Lastpage :
552
Abstract :
Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications. Commonly, CGRAs are composed of a computation layer (that performs computations) and a memory layer (that provides data and config ware to the computation layer). Tempted by higher platform utilization and reliability, recently proposed CGRA soffer dynamic application remapping (for the computation layer). Distributed scratch pad (compiler programmed) memories offer high data rates, predictability and low the power consumption (compared to caches). Therefore, the distributed scratchpad memories are emerging as preferred implementation alternative for the memory layer in recent CGRAs. However, the scratchpad memories are programmed at compile time, and do not support dynamic application remapping. The existing solutions that allow dynamic application remapping either rely on fat binaries (that significantly enhance configuration memory requirements) or consider a centralized memory. To extract the benefits of both runtime remapping and distributed scratchpad memories, we present a design framework called DyMeP. DyMeP relies on late binding and provides the architectural support to dynamically remap data in CGRAs. Compared to the state of the art, the proposed technique reduces the configuration memory requirements (needed by fat binary solutions) and supports distributed shared scratchpad memory. Synthesis/Simulation results reveal that DyMeP promises a significant (up to 60%) reduction in config ware size at the cost of negligible additional overheads (less then 1%).
Keywords :
distributed shared memory systems; reconfigurable architectures; storage management; CGRAs; DyMeP; coarse grained reconfigurable architectures; compiler programmed memories; computation layer; distributed shared scratchpad memories; dynamic application remapping; dynamic memory binding; fat binaries; memory layer; runtime mapping; Delays; Dynamic scheduling; Hardware; Memory management; Routing; Runtime; Synchronization; CGRA; Coarse Grained Reconfigurable Architecture; Dynamic Memory Binding; NOC; Network on Chip; circuit switched network on chip; late binding; relative addressing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2015.98
Filename :
7031792
Link To Document :
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