• DocumentCode
    3438393
  • Title

    An efficient algorithm for real-time symbolic model checking

  • Author

    Frossl, J. ; Gerlach, Joachim ; Kropf, Th

  • Author_Institution
    Inst. fur Rechnerentwurf und Fehlertoleranz, Karlsruhe Univ., Germany
  • fYear
    1996
  • fDate
    11-14 Mar 1996
  • Firstpage
    15
  • Lastpage
    20
  • Abstract
    The verification of real-time properties requires model checking techniques for quantitative temporal structures and real-time temporal logics. However, up to now, most of those problems were solved by a translation into a standard CTL model checking problem with unit-delay structures. Although usual CTL model checkers like SMV can be used then, the translation leads to large structures and CTL formulas, such that the verification requires large computation times and only small circuits can be verified. In this paper a new model checking algorithm for quantitative temporal structures and quantitative temporal logic is presented, which avoids these drawbacks. Motivated by low level circuit verification, the implemented prover can be used for verifying general real-time systems. Although it has been proved that the complexity of the new algorithm is identical to the corresponding CTL model checking problem, the application of the new algorithms leads to significant better runtimes and larger verifiable structures. The paper presents the underlying algorithms, the complexity proof, implementational issues and concludes with experimental results, demonstrating the advantages of our approach
  • Keywords
    Boolean functions; circuit analysis computing; computational complexity; formal verification; logic CAD; real-time systems; temporal logic; complexity proof; low level circuit verification; model checking algorithm; quantitative temporal logic; quantitative temporal structures; real-time symbolic model checking; Automata; Boolean functions; Circuits; Clocks; Delay; Hardware; Logic; Real time systems; Runtime; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    European Design and Test Conference, 1996. ED&TC 96. Proceedings
  • Conference_Location
    Paris
  • ISSN
    1066-1409
  • Print_ISBN
    0-8186-7424-5
  • Type

    conf

  • DOI
    10.1109/EDTC.1996.494120
  • Filename
    494120