Title :
RISC architecture of the M88000
Author_Institution :
Motorola, Austin, TX, USA
Abstract :
The 88000 processor family is one of the RISC (reduced-instruction-set computer) microcomputers that integrate the integer execution unit, the floating-point unit, the instruction fetch pipelines, and a data memory unit interface onto a single device. There are many supporting structures, such as advance branch target address calculation, dedicated units for memory address calculation, and bit field shifters to increase system performance. The 88000 device is structured such that each unit can perform concurrently, i.e. floating-point, integer, and data access instructions can all be being executed simultaneously while other instructions are being fetched. The author examines the 88000 machine to see how computing performance is gained through architectural enhancements
Keywords :
microcomputers; reduced instruction set computing; M88000; RISC architecture; bit field shifters; data memory unit interface; floating-point unit; instruction fetch pipelines; integer execution unit; memory address calculation; microcomputers; Circuits; Clocks; Computer aided instruction; Computer architecture; Hardware; Manufacturing processes; Microcomputers; Reduced instruction set computing; Registers; Silicon;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25725
