First 32-bit SPARC-based processors implemented in high-speed CMOS

The author presents an overview of the first two implementations of Sun Microsystems´s scalable processor architecture (SPARC). The first implementation, MB86900, is designed using a 20000-gate 1.3-μm CMOS gate-array. It operates at a clock rate of 16.6 MHz and delivers an average performance of 10 integer MIPS (millions of instruction per second). The second, CY7C601, is a full custom chip designed using a 0.8-μm CMOS process. It operates at a clock rate of 33 MHz and delivers an average performance of 20 integer MIPS. The author discusses the basic features of these processors, their similarities and differences, and the tradeoffs used in their design. He also discusses the issues of design verification, test generation, and fault simulation