Synthesis from VHDL

The VHDL Synthesis System (VSS) uses VHDL dataflow or behavioral descriptions as input and outputs a structural description of generic components. This structural description is converted into a schematic and captured by the microarchitecture and logic optimization system for technology mapping and constraint-driven optimization. VSS allows a designer to modify the compiled design by changing the input description, selecting optimization and mapping strategies, or graphically changing the generated design schematic. Redesign to new technologies can be accomplished by changing only the component library