High-linearity calibration of low-resolution digital-to-analog converters

Author

Goes, J. ; Franca, J. ; Paulino, N. ; Grilo, J. ; Temes, G.

Author_Institution

Integrated Circuits & Syst. Group, Inst. Superior Tecnico, Lisbon, Portugal

Volume

5

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

345

Abstract

We describe a high-precision calibrating system where the code error voltages of a low-resolution binary-weighted capacitor-array DAC, measured against the precise code voltage references generated by a single-capacitor pulse-counting DAC, are digitized and corrected using a small subbinary-weighted capacitor-array. Computer simulation results are given to demonstrate the operation of the proposed system and the benefits that can be gained by employing gain- and offset-compensated stages

Keywords

calibration; digital-analogue conversion; error correction codes; binary-weighted capacitor-array DAC; code error voltages; code voltage references; gain-compensated stages; high-linearity calibration; low-resolution digital-to-analog converters; offset-compensated stages; single-capacitor pulse-counting DAC; subbinary-weighted capacitor-array; Calibration; Capacitors; Computer architecture; Digital-analog conversion; Error correction codes; Linearity; Pulse amplifiers; Pulse generation; Pulse measurements; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409378

Filename

409378