High-level synthesis of recoverable microarchitectures

Author

Ohm, Seong Y. ; Blough, Douglas M. ; Kurdahi, Fadi J.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA

fYear

1996

fDate

11-14 Mar 1996

Firstpage

55

Lastpage

62

Abstract

Two algorithms that combine the operations of scheduling and recovery point insertion for high-level synthesis of recoverable microarchitectures are presented. The first uses a prioritized cost function in which functional unit cost is minimized first and register cost second. The second algorithm minimizes a weighted sum of functional unit and register costs. Both algorithms are optimal according to their respective cost functions and require less than 10 minutes of CPU time on widely-used high-level synthesis benchmarks. The best previous result reported several hours of CPU time for some of the same benchmarks

Keywords

data flow graphs; digital systems; high level synthesis; reconfigurable architectures; scheduling; CDFG; benchmarks; control and data flow graph; fault-tolerant digital systems; functional unit cost; high-level synthesis; prioritized cost function; recoverable microarchitectures; recovery point insertion; register cost; scheduling; weighted sum; Application software; Cost function; Digital systems; Fault tolerant systems; Hardware; High level synthesis; Microarchitecture; Processor scheduling; Registers; Scheduling algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494128

Filename

494128