Estimation of area and performance overheads for testable VLSI circuits

A method of estimating the area required to improve the testability of integrated circuits is described, and is illustrated by reference to programmable logic arrays (PLAs) with scan path applied. Parameters used in the models are derived from actual layouts. Results are given for PLAs with scan path, and for static RAMs incorporating scan path and built-in self-test (BIST) techniques. A stochastic model for estimating the global routing required on integrated circuits is presented, with results showing its use for predicting the routing area overhead due to test circuitry. A method of predicting the increased signal propagation delay due to added test circuitry is also given, together with the conditions for determining degradation in chip performance