Title :
Estimation of area and performance overheads for testable VLSI circuits
Author :
Miles, J.R. ; Ambler, A.P. ; Totton, K.A.E.
Author_Institution :
Dept. of Electr. Eng. & Electron., Brunel Univ., Uxbridge, UK
Abstract :
A method of estimating the area required to improve the testability of integrated circuits is described, and is illustrated by reference to programmable logic arrays (PLAs) with scan path applied. Parameters used in the models are derived from actual layouts. Results are given for PLAs with scan path, and for static RAMs incorporating scan path and built-in self-test (BIST) techniques. A stochastic model for estimating the global routing required on integrated circuits is presented, with results showing its use for predicting the routing area overhead due to test circuitry. A method of predicting the increased signal propagation delay due to added test circuitry is also given, together with the conditions for determining degradation in chip performance
Keywords :
VLSI; automatic testing; circuit layout CAD; integrated circuit testing; logic arrays; logic testing; random-access storage; area estimation; built-in self-test; chip performance; global routing; layouts; performance overheads; programmable logic arrays; signal propagation delay; static RAMs; stochastic model; testability; testable VLSI circuits; Built-in self-test; Circuit testing; Integrated circuit modeling; Integrated circuit testing; Logic circuits; Logic testing; Programmable logic arrays; Routing; Stochastic processes; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25732
