CESAR-A programmable high performance systolic array processor

Author

Toverud, Morten ; Anderson, V.

Author_Institution

Norwegian Defence Res. Establ., Kjeller, Norway

fYear

1988

fDate

3-5 Oct 1988

Firstpage

414

Lastpage

417

Abstract

The authors describe the architecture and implementation of the CESAR computer system. The computing unit in CESAR has from one to four programmable systolic arrays working strictly in parallel, representing a SIMD (single-instruction multiple-data) structure. Each array consists of 128 custom-designed processing elements individually programmable for performing bit-serial operations on 32-bit data. Including control logic and memory units, a complete CESAR system with four systolic arrays is implemented on 13 circuit boards. Care has been taken to build in testability at all levels. Originally developed for processing of images from synthetic aperture radar, CESAR is also available for other applications demanding extensive vector processing

Keywords

computer architecture; parallel processing; 32-bit data; CESAR; SIMD; computer architecture; programmable high performance systolic array processor; vector processing; Application software; Computer aided instruction; Computer architecture; Concurrent computing; Delay; Hardware; Pipeline processing; Synchronization; Synthetic aperture radar; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25734

Filename

25734