Title :
Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs
Author :
Mohapatra, Nihar R. ; Mahapatra, S. ; Rao, V. Ramgopal ; Shukuri, S. ; Bude, J.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay, India
fDate :
30 March-4 April 2003
Abstract :
The effect of programming biases on the cycling endurance of NOR flash EEPROMs is studied under CHE and CHISEL operation. CHE degradation increases at higher control gate bias (VCG) and is insensitive to changes in drain bias (VD) CHISEL degradation is insensitive to changes in both VCG, and VD. Furthermore, CHISEL always shows lower degradation when compared to CHE under identical bias and similar programming time. The possible physical mechanisms responsible for the above behavior are clarified by using full band Monte-Carlo simulations.
Keywords :
CMOS memory circuits; Monte Carlo methods; NOR circuits; PLD programming; circuit simulation; flash memories; hot carriers; integrated circuit reliability; CHE degradation; CHE flash EEPROMs; CHISEL flash EEPROMs; NOR flash EEPROMs; channel hot electron injection; channel initiated secondary electron injection; control gate bias; cycling endurance; drain bias changes; full band Monte-Carlo simulations; physical mechanisms; programming biases; programming time; reliability; Channel hot electron injection; Degradation; EPROM; Energy consumption; Hot carriers; Integrated circuit reliability; Integrated circuit technology; Nonvolatile memory; Substrate hot electron injection; Threshold voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197802
