Design of time delay controller based on variable reference model

Many plants have upper and lower bounds beyond which saturation of control efforts occurs. Since the saturation adversely affects control performance, it should be avoided if possible. In the paper an approach of avoiding saturation by varying the reference model for time delay control based systems subject to the step changes in reference inputs. In this scheme, the variable reference model is determined based on the information on control inputs and the size of the step changes in the reference inputs. This scheme is verified by application to the position control experiments using