DocumentCode
3438751
Title
A processor with list structured memory
Author
Rounce, P.A.
Author_Institution
Dept. of Comput. Sci., Univ. Coll., London, UK
fYear
1991
fDate
13-16 May 1991
Firstpage
41
Lastpage
45
Abstract
The Sprint processor and its list-structured memory are discussed. The memory structure and its special features are also described. An examination is made of how this style of memory has been supported on standard memories and the implementation of the Sprint processor
Keywords
CMOS integrated circuits; integrated memory circuits; list processing; microprocessor chips; Sprint processor; list structured memory; Computer architecture; Computer science; Density measurement; Educational institutions; Hardware; Kernel; Memory architecture; Message passing; Operating systems; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location
Bologna
Print_ISBN
0-8186-2141-9
Type
conf
DOI
10.1109/CMPEUR.1991.257353
Filename
257353
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