VLSI architecture for size-orientation-invariant pattern recognition

Author

Cheng, H.D. ; Tang, Yuan Y. ; Suen, Ching Y.

Author_Institution

Sch. of Comput. Sci., Tech. Univ. of Nova Scotia, Halifax, NS, Canada

fYear

1991

fDate

13-16 May 1991

Firstpage

63

Lastpage

67

Abstract

A programmable VLSI architecture is proposed to perform size-rotation-invariant pattern recognition. The architecture is an array of processing elements (PEs) and the connections among the PEs can be reconfigured to meet the different requirements of the different computation stages. The merits of the proposed transformation ring-projection algorithm are its lower time complexity, higher accuracy and greater stability than existing algorithms. The results indicate that the proposed algorithm and VLSI architecture can be very useful to real-time pattern recognition and image processing

Keywords

VLSI; computerised pattern recognition; digital signal processing chips; invariance; accuracy; feature extraction; image normalization; image processing; programmable VLSI architecture; real-time pattern recognition; size-orientation-invariant pattern recognition; size-rotation-invariant pattern recognition; stability; time complexity; transformation ring projection; Computer architecture; Computer science; Costs; Delay effects; Hardware; High performance computing; Image processing; Parallel algorithms; Pattern recognition; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257357

Filename

257357