VLSI architecture for size-orientation-invariant pattern recognition

A programmable VLSI architecture is proposed to perform size-rotation-invariant pattern recognition. The architecture is an array of processing elements (PEs) and the connections among the PEs can be reconfigured to meet the different requirements of the different computation stages. The merits of the proposed transformation ring-projection algorithm are its lower time complexity, higher accuracy and greater stability than existing algorithms. The results indicate that the proposed algorithm and VLSI architecture can be very useful to real-time pattern recognition and image processing