DocumentCode
3438847
Title
A timing-constrained incremental routing algorithm for symmetrical FPGAs
Author
Raman, Srilata ; Liu, C.L. ; Jones, L.G.
Author_Institution
Adv. Design Technol., Motorola Inc., Austin, TX, USA
fYear
1996
fDate
11-14 Mar 1996
Firstpage
170
Lastpage
174
Abstract
in this paper we present a timing-constrained routing algorithm for symmetrical FPGAs which embodies a novel incremental routing strategy that combines global and detailed routing, and a routing resource allocation algorithm that takes into account both the characteristics of the routing resources and timing information. Experimental results confirm that the algorithm reduces delay along the longest path in the circuit, uses routing resources efficiently, and requires low CPU time
Keywords
field programmable gate arrays; integrated circuit layout; logic design; network routing; resource allocation; timing; circuit delay; detailed routing; global routing; resource allocation; symmetrical FPGAs; timing-constrained incremental routing algorithm; Delay estimation; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Pins; Resource management; Routing; Switches; Symmetric matrices; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location
Paris
ISSN
1066-1409
Print_ISBN
0-8186-7424-5
Type
conf
DOI
10.1109/EDTC.1996.494144
Filename
494144
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