DocumentCode :
3439064
Title :
Design and selection of buffers for minimum power-delay product
Author :
Turgis, S. ; Azemard, N. ; Auvergne, D.
Author_Institution :
Lab. d´´Inf. de Robotique et de Mictroelectron., CNRS, Montpellier, France
fYear :
1996
fDate :
11-14 Mar 1996
Firstpage :
224
Lastpage :
228
Abstract :
Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to a standard cell library in comparing implementations for different selection alternatives
Keywords :
CMOS logic circuits; buffer circuits; delays; integrated circuit design; logic design; CMOS buffers; SPICE simulations; buffer design; buffer insertion limit; buffer selection; explicit delay modeling; minimum power-delay product; power dissipation; standard cell library; two stage inverter arrays; Capacitance; Delay effects; Equations; Inverters; Libraries; Power dissipation; Propagation delay; Robots; SPICE; Semiconductor device modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7424-5
Type :
conf
DOI :
10.1109/EDTC.1996.494153
Filename :
494153
Link To Document :
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