Area evaluation metrics for transistor placement

The authors report a quantitative comparison of area evaluation metrics for CMOS transistor placement, along with a novel analysis technique to determine their absolute merit. The transistor placer TOPOLOGIZER was used to generate test case placements. The resolution of transistor placement algorithms based on metrics (e.g. simulated annealing, branch and bound) are limited to the resolution of the metric. The best metric studied was only able to correctly identify, with 90% accuracy, the better of two placements whose layout areas differed by more than 30%