A complex multiplier with low logic depth

Author

Berkeman, Anders ; Owall, Viktor ; Torkelson, Mats

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

Volume

3

fYear

1998

fDate

1998

Firstpage

47

Abstract

A complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is approximately 100%. For verification, the multiplier is currently under fabrication in a three metal-layer 0.5 μm CMOS process using a standard cell library

Keywords

CMOS logic circuits; adders; digital signal processing chips; distributed arithmetic; fast Fourier transforms; multiplying circuits; pipeline processing; 0.5 micron; Wallace-trees; complex multiplier; critical path; distributed arithmetic; low logic depth; pipelined FFT processor; processor throughput; short input to output delay; simulated gain in speed; standard cell library; three metal-layer CMOS process; Arithmetic; Clocks; Delay; Energy consumption; Fabrication; Fast Fourier transforms; Logic arrays; Pipelines; Process design; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813933

Filename

813933