Title :
Timing analysis using propositional satisfiability
Author :
Silva, L.G. ; Silva, Joao M. ; Silveira, Luís Miguel ; Skallah, K.A.
Author_Institution :
INESC, Inst. Superior Tecnico, Lisbon, Portugal
Abstract :
The existence of false paths represents a significant and computationally complex problem in the timing analysis of combinational and sequential circuits. In this paper we describe propositional satisfiability based algorithms for timing analysis, which introduce significant perfomance improvements over existing procedures. In particular we address the problems of circuit delay computation and path delay validation, describing algorithms and providing experimental results for both problems
Keywords :
circuit analysis computing; combinational circuits; computability; delay estimation; sequential circuits; timing; circuit delay computation; combinational circuits; false paths; path delay validation; propositional satisfiability; sequential circuits; timing analysis; Algorithm design and analysis; Circuit analysis computing; Clocks; Combinational circuits; Delay estimation; Digital circuits; Frequency estimation; Laboratories; Sequential circuits; Timing;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.813943
