Handling faults in a VLSI CAD environment

Author

Calia, Edoardo ; Lioy, Antonio

Author_Institution

Dipartimento di Autom. e Inf., Politecnico di Torino, Italy

fYear

1991

fDate

13-16 May 1991

Firstpage

219

Lastpage

223

Abstract

A tool to generate target fault sets for fault simulation and test pattern generation is described. It can deal with circuits described hierarchically and at multiple levels of abstraction (switch, gate, and register transfer), using a uniform fault model and a fast collapsing algorithm. Whenever possible, structurally undetectable faults are identified. A flexible user-friendly interface provides hierarchical, functional, and statistical selection commands to customize a fault set according to the user´s needs

Keywords

VLSI; circuit CAD; digital simulation; failure analysis; integrated circuit testing; user interfaces; VLSI CAD environment; fast collapsing algorithm; fault set customization; fault simulation; functional selection commands; gate level; hierarchical selection commands; hierarchically described circuits; multiple abstraction levels; register transfer level; statistical selection commands; structurally undetectable faults; switch level; target fault sets; test pattern generation; uniform fault model; user-friendly interface; Automatic test pattern generation; Circuit faults; Circuit simulation; Circuit testing; Conductivity; Logic gates; Logic testing; Switches; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257385

Filename

257385