A testable PLA design with low overhead and ease of test generation

The author presents a hybrid programmable-logic array (PLA) design-for-testability technique that requires negligible hardware overhead and still preserves the property of ease of test generation. The key idea is to further utilize the `don´t care´ assignment by introducing the control of both true and complement bits of some inputs to meet the requirement of distance-2 test sets. This approach is applied to the BARNEW PLA, and results support the claim that the hardware overhead of this technique is negligible and the ease of test generation is preserved