DocumentCode
3439958
Title
Fault-tolerance: new trends for digital circuits
Author
dos Santos, JoseMiguel Vieira ; Ferreira, Jose Manuel Martins
Author_Institution
FEUP/ISEP, Porto, Portugal
Volume
3
fYear
1998
fDate
1998
Firstpage
237
Abstract
Fault-tolerance usually means expensive designs. The solution proposed by the authors allows fault detection in cost effective designs, with a small overhead, and may also correct some output patterns providing a discrete fault-tolerance
Keywords
boundary scan testing; digital integrated circuits; fault tolerance; integrated circuit reliability; integrated circuit testing; logic testing; boundary scan test; concurrent testing; cost effective designs; digital circuits; discrete fault-tolerance; fault detection; output pattern correction; Binary search trees; Circuit faults; Circuit testing; Computer bugs; Costs; Digital circuits; Electrical fault detection; Fault detection; Fault tolerance; Hardware;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location
Lisboa
Print_ISBN
0-7803-5008-1
Type
conf
DOI
10.1109/ICECS.1998.813975
Filename
813975
Link To Document