RISC-based coprocessor with a dedicated VLSI neural network

In this paper, a multilayer perceptron, so called the DMNN (Digital Multilayer Neural Network), is designed in VLSI. The DMNN has a modular architecture leading to an effective hardware implementation of multiple multilayer perceptrons. Any size of the DMNN can be built using basic modules implemented using FPGAs. The architecture of a RISC-based coprocessor including the DMNN unit, a control and interface unit, a memory unit, etc., is also developed. The coprocessor is modeled in VHDL and synthesized. Pattern recognition problems are applied to the DMNN coprocessor to justify its applicability to real engineering problems