An analog CMOS realisation of a reconfigurable discrete-time cellular neural network

Author

Brea, V.M. ; Vilarino, D.L. ; Cabello, D.

Author_Institution

Dept. of Electron. & Comput. Sci., Santiago de Compostela Univ., Spain

Volume

3

fYear

1998

fDate

1998

Firstpage

285

Abstract

In this work we propose a new analog CMOS realisation of a cell structure for a Discrete-Time Cellular Neural Network (DTCNN) with a view to implementing a multilayer network for image segmentation based on active contours. Each cell operates in a transresistance manner with a final latch controlled by a single clock phase. The operation with the templates, for the calculation of internal states is provided by voltage programmable current multipliers. The validity of the structure is illustrated by electric HSPICE simulations for an 8×8 DTCNN array, constituted by transistors belonging to the 0.7 μm technology process of ES2

Keywords

CMOS analogue integrated circuits; SPICE; cellular arrays; circuit simulation; digital simulation; discrete time systems; image segmentation; multilayer perceptrons; neural net architecture; reconfigurable architectures; 0.7 mum; Discrete-Time Cellular Neural Network; HSPICE simulation; active contours; analog CMOS; image segmentation; internal states; multilayer network; reconfigurable discrete-time cellular neural network; single clock phase; transresistance; voltage programmable current multipliers; Active contours; Cellular neural networks; Circuits; Clocks; Computer science; Electronic mail; Image segmentation; Latches; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813988

Filename

813988