Title :
Fault-tolerant mapping algorithms onto hardware structure of a multiprocessor system
Author_Institution :
Inst. of Inf. Transmission Problems, Acad. of Sci., Moscow, USSR
Abstract :
An approach to ensuring fault-tolerance of multiprocessor systems is presented. The approach is based on arranging computations in a system in such a way that in the presence of faults of some processing modules (PMs) the tasks (which have to be executed by the system) can be reassigned for execution between the remaining nonfaulty PMs, thereby reactivating the system. This reactivation may be performed with the system operation quality degraded within acceptable limits. The problem of developing the methods of task reassignment (TR) which meet system requirements for fault-tolerance and optimize the given parameters of the system operation quality are considered. This goal is achieved by means of fault-tolerant mapping algorithms (which have to be executed by the system) onto its hardware structure
Keywords :
fault tolerant computing; multiprocessing systems; multiprocessor interconnection networks; fault-tolerance; fault-tolerant mapping algorithms; hardware structure; multiprocessor system; processing modules; system operation quality; system reactivation; task reassignment; Artificial intelligence; Control systems; Fault tolerance; Fault tolerant systems; Hardware; Multiprocessing systems; Performance evaluation; Q factor; Q measurement;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257426
