Title :
Implementation criteria for a high-speed parallel banyan switch
Author :
Masetti, F. ; Raffaelli, C.
Author_Institution :
Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
Abstract :
A broadband switch architecture is proposed which is obtained by buffered banyan multistage networks working in parallel on fractions of the same packet, with the main purpose of implementing a very high-speed switch using present-day technology. The most novel element is the design of a flexible switch with parallel banyan networks, each being a fully independent subswitch. The main characteristics of this architecture are outlined, with particular attention given to the obtainable switch rate and flexibility. Switch reliability is then analyzed through numerical evaluation of the alignment loss probability due to fraction routing errors. The implementation details of two application examples are described to show the feasibility of broadband switches based on the proposed architecture with current technology
Keywords :
multiprocessor interconnection networks; parallel architectures; alignment loss probability; broadband switch architecture; buffered banyan multistage networks; flexible switch; fraction routing errors; parallel banyan networks; parallel banyan switch; switch reliability; Bit rate; Clocks; Communication switching; Frequency; Optical buffering; Optical losses; Optical packet switching; Optical switches; Packet switching; Routing;
Conference_Titel :
CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.
Conference_Location :
Bologna
Print_ISBN :
0-8186-2141-9
DOI :
10.1109/CMPEUR.1991.257434
