InP-based logic gates for low power monolithic optoelectronic circuits [InGaAs/InAlAs/InP]

Author

Brennemann, A. ; Bushehri, E. ; Daumann, W. ; Agethen, M. ; Bertenburg, R.M. ; Brockerhoff, W. ; Staroselsky, V. ; Bratov, V. ; Schlichter, T. ; Tegude, F.-J.

Author_Institution

Dept. of Solid State Electron., Gerhard-Mercator-Univ., Duisburg, Germany

Volume

3

fYear

1998

fDate

1998

Firstpage

393

Abstract

This paper describes the InP-based HFET technology for the implementation of high bitrate logic gates. A novel logic gate configuration is presented based on depletion mode HFETs (DHFET) using a nonlinear negative feedback (NNFB) for optimized high speed operation. The NNFB increases the switching speed of the gates while reducing the logic HIGH output level. The functionality of this logic design approach is demonstrated in InP with an 11-stage inverter chain and an output buffer. The realization of a ring oscillator and an edge-triggered D-flip-flop are currently in progress

Keywords

III-V semiconductors; aluminium compounds; circuit feedback; field effect logic circuits; gallium arsenide; high-speed integrated circuits; indium compounds; logic gates; optical fibre communication; optical receivers; HFET technology; InGaAs-InAlAs-InP; depletion mode HFETs; edge-triggered D-flip-flop; high bitrate logic gates; inverter chain; logic HIGH output level; logic gate configuration; low power monolithic optoelectronic circuits; nonlinear negative feedback; optimized high speed operation; output buffer; ring oscillator; switching speed; Bit rate; Boolean functions; Data structures; HEMTs; Indium phosphide; Inverters; Logic design; Logic gates; MODFETs; Negative feedback;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.814016

Filename

814016