Title :
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
Author :
Lee, W.-H. ; Waite, A. ; Nii, H. ; Nayfeh, H.M. ; McGahay, V. ; Nakayama, H. ; Fried, D. ; Chen, H. ; Black, L. ; Bolam, R. ; Cheng, J. ; Chidambarrao, D. ; Christiansen, C. ; Cullinan-Scholl, M. ; Davies, D.R. ; Domenicucci, A. ; Fisher, P. ; Fitzsimmons
Author_Institution :
IBM Syst. & Technol. Group, IBM Semicond. Res. & Dev. Center, Hopewell Junction, NY
Abstract :
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting technology delivers pFET and nFET AC switching on-current of 735 muA/mum and 1259 muA/mum respectively, at an off-current of 200 nA/um (Vdd=1.0 V), and 6% reduction in interconnect delay. Process yield is demonstrated on a SRAM cell with size of 0.65 mum2
Keywords :
CMOS integrated circuits; SRAM chips; field effect transistors; integrated circuit interconnections; silicon-on-insulator; 65 nm; SOI CMOS technology; SRAM cell; SiCOH; dual stress liner; field effect transistors; stress memorization; transistor strain; CMOS technology; Capacitive sensors; DSL; Delay; Dielectrics; Germanium silicon alloys; Silicon germanium; Stress; Transistors; Wiring;
Conference_Titel :
Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-9268-X
DOI :
10.1109/IEDM.2005.1609265
